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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Datasheet
The Intel(R) LC Small Form Factor (SFF) optical transceivers are high-performance integrated modules for bi-directional communication over Multimode optical fiber. The Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver (called hereafter the TXN31015D2 Optical Transceiver) is specifically designed for high-speed Fibre Channel data links at 4.25 Gbps (4x Fibre Channel rate). The TXN31015D2 Optical Transceiver is also backwards compatible with 2x and 1x Fibre Channel and Gigabit Ethernet rates. The TXN31015D2 Optical Transceiver has an LC receptacle compatible with the industry-standard LC connector. The TXN31015D2 Optical Transceiver is Class 1 laser safety compliant with FDA Radiation Performance Standards, 21 CFR 1040.10, and international standards IEC 60825-1 and IEC 60825-2.
Product Features
Compliant with the Fibre Channel FC-PI Standard 4.25/2.125/1.0625 Gbps Fibre Channel and 1.25 Gbps Ethernet Compatible Compatible with the SFF Multisource Agreement (MSA) Specification 850 nm VCSEL emitter TTL Signal Detect Output Transmitter Disable Input AC-coupled CML Level Input/Output Single +3.3 V Power Supply Class 1 Laser Safety Product IEC/UL 60950-1 Safety Certified Designed and verified as RoHS 6 compliant China RoHS compliant with 30-year EFUP Digital Diagnostics Support
Applications
Fibre Channel Host Bus Adapters iSCSI Host Bus Adapters Ethernet Network Interface Cards
Order Number:316366 , Revision: 001US 18-April-2007
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Legal Lines and Disclaimers
Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. The Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2007, Intel Corporation. All Rights Reserved.
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 2
18-April-2007 Order Number:316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Contents
1.0 2.0 Introduction .............................................................................................................. 7 Specifications ............................................................................................................ 8 2.1 Maximum Ratings and Recommended Operating Conditions ...................................... 8 2.2 Electrical Characteristics....................................................................................... 9 Electrical Interface .................................................................................................. 12 Termination............................................................................................................. 15 4.1 Types of I/O Interfaces ...................................................................................... 15 4.2 CML Termination ............................................................................................... 15 SFF Timing Parameters............................................................................................ 17 Digital Diagnostic Monitoring Interface ................................................................... 18 6.1 Overview of Digital Diagnostic Monitoring Interface................................................ 18 6.2 General Memory Map Descriptions ....................................................................... 19 6.3 Alarm and Warning Fields for 2-Wire Interface Address A2h .................................... 20 6.4 A/D Fields for 2-Wire Interface Address A2h.......................................................... 22 Grounding Scheme .................................................................................................. 22 Mechanical Specification.......................................................................................... 25 Regulatory Compliance ............................................................................................ 27 9.1 Electromagnetic Compatibility Compliance ............................................................ 27 9.2 Safety Compliance............................................................................................. 28 9.3 Lead-Free Conformance ..................................................................................... 29 9.4 Compliance with Restriction of Hazardous Substances (RoHS) ................................. 29 9.5 Management Methods on Control of Pollution from Electronic Information Products (a.k.a. China RoHS)........................................................................................... 30 9.6 Product Certification Markings and Compliance Statements ..................................... 31
3.0 4.0
5.0 6.0
7.0 8.0 9.0
10.0 Ordering Information .............................................................................................. 32 11.0 Acronyms ................................................................................................................ 33
Figures
2 3 4 5 Pin Layout............................................................................................................... 14 Circuit Diagram for CML Termination on Receiver Output ............................................... 15 Circuit Diagram for CML Termination on Transmitter Input............................................. 16 Grounding Application Diagram for Intel(R) TXN31015D2 Optical Transceiver ..................... 24 SFF Mechanical Specifications .................................................................................... 26
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 3
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Absolute Maximum Ratings ......................................................................................... 8 Recommended Operating Conditions ............................................................................ 8 Electrical Characteristics - Power and Current ............................................................... 9 Electrical Characteristics - Transmitter ......................................................................... 9 Electrical Characteristics - Receiver ............................................................................10 Electrical Characteristics - 2-Wire Interface .................................................................10 Fiber Length Specifications ........................................................................................10 Optical Specifications - Transmitter ............................................................................11 Optical Specifications - Receiver.................................................................................11 Pin Assignment ........................................................................................................12 Timing Parameters for SFF Management ......................................................................17 Memory Map - 2-Wire Address Range Descriptions .......................................................19 Alarm and Warning Fields - 2-Wire Address A2h, Address 0-95 ......................................20 A/D Fields - 2-Wire Address A2h, Addresses 96-109 .....................................................22 A/D Status/Control Bits - 2-Wire Address A2h, Address 110...........................................22 Electromagnetic Compatibility Compliance ..................................................................26 Safety Compliance....................................................................................................27 Lead-Free 2nd-Level Interconnect Markings ..................................................................28 Hazardous Substances Table ......................................................................................29 Product Certification Markings and Compliance Statements ............................................30 Ordering Information ................................................................................................31 Acronyms ................................................................................................................32
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 4
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Revision History
Date 18-April-2007
Revision 001 Initial release of document
Description
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 5
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 6
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
1.0
Introduction
The Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible (called hereafter the TXN31015D2 Optical Transceiver) is specifically designed for high-speed Fibre Channel data links at 4.25 Gbps (4x Fibre Channel rate). This document discusses the following TXN31015D2 Optical Transceiver topics: * Section 2.0, "Specifications" on page 8 * Section 3.0, "Electrical Interface" on page 12 * Section 4.0, "Termination" on page 15 * Section 5.0, "SFF Timing Parameters" on page 17 * Section 6.0, "Digital Diagnostic Monitoring Interface" on page 18 * Section 8.0, "Mechanical Specification" on page 25 * Section 9.0, "Regulatory Compliance" on page 27 * Section 10.0, "Ordering Information" on page 32 * Section 11.0, "Acronyms" on page 33 For information on standards that apply to the TXN31015D2 Optical Transceiver, see the following references: * "Diagnostic Monitoring Interface for Optical Xcvrs". SFF Document Number SFF-8472, Revision 9.3. * IEEE Std 802.3, 2002 Edition, Clause 38, PMD Type 1000BASE-SX. IEEE Standards Department, 2002 * IEEE Std 802.3z, 1998 Edition. Gigabit Interface Converter (GBIC) Ethernet Standard. * Small Form-Factor (SFF) Transceiver Multisource Agreement (MSA) * Telcordia Technologies* GR-63 Section 4.2
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 7
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
2.0
Specifications
Specifications include the following: * Section 2.1, "Maximum Ratings and Recommended Operating Conditions" on page 8 * Section 2.2, "Electrical Characteristics" on page 9 * Section , "Table 5 lists the TXN31015D2 Optical Transceiver receiver electrical characteristics. Table 6 lists the TXN31015D2 Optical Transceiver 2-Wire Interface electrical characteristics. Optical Specifications" on page 10
2.1
Maximum Ratings and Recommended Operating Conditions
Table 1 lists the absolute maximum ratings for the TXN31015D2 Optical Transceiver.
Table 1.
Absolute Maximum Ratings
Parameter Storage Temperature Relative Humidity Soldering Temperature Supply Voltage Data AC Voltage Control Input Voltage Symbol Ts RH - VccT, R TD+ and TDVi Min -40 5 - -0.5 - -0.5 Typ - - - - - - Max 85 95 260 4 2.2 Vcc + 0.3 Units C % C V Vpp V Notes - - 10 seconds on leads only - Differential -
Caution:
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Table 2 lists the recommended operating conditions. (Minimum and maximum values listed in Table 3 through Table 9 apply over the recommended operating conditions specified in Table 2.) Table 2. Recommended Operating Conditions
Parameter Case Temperature Supply Voltage Data Rate Symbol Tc VccT, R - Min -20 2.97 1.0625 Typ - 3.3 - Max 85 3.63 4.25 Units C VDC Gbps
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 8
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
2.2
Electrical Characteristics
The minimum and maximum values in this section apply over the following recommended temperature and voltage range (from Table 2, "Recommended Operating Conditions" on page 8). -20 C < Tc < 85 C, 3.0 V < Vcc < 3.6 V Table 3 lists the TXN31015D2 Optical Transceiver electrical characteristics for power and current.
Table 3.
Electrical Characteristics - Power and Current
Parameter Supply Current Power Dissipation Supply Noise Rejection Symbol lcc Pdiss - Min - - 100 Typ 170 - 565 - 220 800 - Max Units mA mA mW mV Notes Tc = 20C, Vcc = 3.3 V - - 10 kHz to 4 MHz with supply filter
Table 4 lists the TXN31015D2 Optical Transceiver transmitter electrical characteristics. Table 4. Electrical Characteristics - Transmitter
Parameter CML Input (Single Ended) CML Input (Differential) Input Impedance (differential) TX_DISABLE input voltage High TX_DISABLE input voltage Low TX_Fault Output Voltage High TX_Fault Output Voltage Low Symbol - - ZIN VIH VIL VOH VOL Min 250 500 85 2 0 2.0 0 Typ - - 100 - - - - Max 1100 2200 115 Vcc + 0.3 0.6 Vcc + 0.3 0.8 Units mVpp mVpp V V V V Notes AC coupled inputs Peak-to-peak voltage - - - IOH = 40 A, 1 TTL Unit Load IOL = -1.6 mA, 1 TTL Unit Load
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Table 5 lists the TXN31015D2 Optical Transceiver receiver electrical characteristics. Table 5. Electrical Characteristics - Receiver
Parameter CML Output (Single Ended) CML Output (Differential) CML Output rise/fall time Output Impedance (differential) TTL Signal Detect Output Low TTL Signal Detect Output High Deterministic Jitter Total Jitter Symbol - - - Zout - VOH DJ TJ - - Min 250 500 - 85 0 2.0 Typ 300 600 - 100 - - Max 500 1000 115 115 0.8 VCC + 0.3 28.2 61.7 Units mVpp mVpp ps V V ps ps Notes AC-coupled outputs Peak-to-peak voltage 20% - 80% - IOL = -1.6 mA, 1 TTL Unit Load IOL = 40 A, 1 TTL Unit Load - -
Table 6 lists the TXN31015D2 Optical Transceiver 2-Wire Interface electrical characteristics. Optical Specifications Table 6. Electrical Characteristics - 2-Wire Interface
Parameter Symbol VOH MOD_DEF (0:2) VOL NC Min 2.5 0 100 K Typ - - - Max VCC + 0.3 0.5 - Units V V Notes With Serial ID - Measured to RGND/ TGND
Table 7 lists the TXN31015D2 Optical Transceiver fiber length specifications. Table 7. Fiber Length Specifications
Parameter Symbol Min Typ 1.0625, 1.25, 2.125, 4.25 10-12 2 - 500 300 150 300 150 70 m Max Units Notes
Data rate
BR
Gbps
1
Bit Error Rate 50 m/125 m MMF
BER L
5 2 3 4 2 3 4
62.5 m/125 m MMF
L
2
-
m
NOTES: 1. 1000BASE-SX compatible per IEEE802.3 and 1x, 2x, and 4x Fibre Channel compatible per FC-PI-2 2. Data rates at 1000BASE-SX Gigabit Ethernet and 1.0625 Gbps 3. Data rates at 2.125 Gbps Fibre Channel. 4. Data rate at 4.25 Gbps Fibre Channel. 5. Data rate at 4.25 Gbps with 27 - 1 PRBS pattern.
Table 8 lists the TXN31015D2 Optical Transceiver transmitter optical specifications.
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 10
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Table 8.
Optical Specifications - Transmitter
Parameter Optical Transmit Power (50 or 62.5 m MMF) Optical Center Wavelength Spectral Width Optical Modulation Amplitude Relative Intensity Noise Deterministic Jitter Total Jitter Output Rise/Fall Time - OMA RIN DJ TJ tR, tF - - - - Symbol Popt Min -8 830 - 247 - Typ -5 850 - - - Max -1.1 860 0.85 - -118 28.2 59.8 90 Units dBm nm nm W dB/Hz ps ps ps Notes Average launch power - RMS pk-pk - - - 20 - 80% values, measured unfiltered
Eye Mask: Compliant with eye mask requirements of Fibre Channel - Physical Interfaces (FC-PI-2) specifications, IEEE 802.3z* Gigabit Ethernet 1000 BASE-SX standard
Table 9 lists the TXN31015D2 Optical Transceiver receiver optical specifications. Table 9. Optical Specifications - Receiver
Parameter Optical Input Wavelength Symbol - Min 770 Typ - Max 860 Units nm - 1.0625 and 2.125 Gbps Test conditions: * 10-12 BER * 9 dB ER input * 27 - 1 PRBS 4.25 Gbps Test conditions: * 10-12 BER * 9 dB ER input * 27 - 1 PRBS Notes
-18
-20
-
dBm
Receiver Sensitivity
Pr
-16
-18
-
dBm
Stressed Sensitivity Receiver Overload Optical Return Loss Signal Detect Asserted Signal Detect - Deasserted Signal Detect Hysteresis
Compliant with Fibre Channel - Physical Interfaces (FC-PI-2) specifications, IEEE 802.3z Gigabit Ethernet 1000 BASE-SX standard - ORL Pa Pd Pa - Pd - 12 - -29 1 - 30 - - - 0 - -17 - 5 dBm dB dB dBm dB - - Measured on transition low to high Measured on transition high to low -
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
3.0
Electrical Interface
Table 10 lists the pin assignment and function descriptions. Table 10. Pin Assignment (Sheet 1 of 2)
Pin Number Pin Name Pin Function Note
1 2 3 4 5 6 7 8 9 10 A B
VeeR VccR SD RDRD+ VccT VeeT TDis TD+ TDMOD-DEF[2] MOD-DEF[1]
Receiver Signal ground Receiver +3.3 V Power Supply Signal Detect TTL output Receiver CML Inverted Data output Receiver CML Data output Transmitter +3.3 V Power Supply Transmitter Signal Ground Transmit Disable TTL input Transmit CML Data input Transmit Inverted CML Data input 2-Wire Serial data TTL input 2-Wire Serial Clock TTL input
Note 1 Note 2 Note 3 Note 4 Note 4 Note 2
Note 1
Note 5 Note 6 Note 6 Note 7 Note 7
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 12
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Table 10.
Pin Assignment (Sheet 2 of 2)
Pin Number C D - Transmit Fault Indication Pin Name Pin Function Not used Tx Fault output - Note 8 Note
NOTES: 1. VeeR and VeeT are the signal grounds, there 2 grounds are internally separated within the SFF module. 2. VccR and VccT are the receiver and transmitter power supplies. Their values, which are listed in Table 2, "Recommended Operating Conditions" on page 8, are defined at the SFF pin assignment. Maximum supply current is listed in Table 3, "Electrical Characteristics - Power and Current" on page 9. 3. SD (Signal Detect) is a TTL output and has an internal 10K pull-up resistor to VccR. * When low, this output indicates the received optical power is below the worst-case receiver sensitivity. In the low state, the output is pulled to < 0.8V. * When high, this output indicates normal operation (as defined by the standard in use). 4. RD-/+ are the differential receiver outputs. They are AC-coupled 100 W differential lines that are terminated with 100 W (differential) at the user SerDes. The AC coupling is performed inside the TXN31015D2 Optical Transceiver and is therefore not required on the host board. 5. TX DISABLE is a TTL input used to shut down the transmitter optical output. The states are as follows: * Low (0 - 0.6 V): Transmitter Enabled * (>0.8, <2.0 V): Undefined * High (2.0 - 3.465 V): Transmitter Disabled 6. TD-/+ are the differential transmitter inputs. They are AC-coupled differential lines with 100 W differential termination inside TXN31015D2 Optical Transceiver. The AC coupling is performed inside the TXN31015D2 Optical Transceiver and is therefore not required on the host board. 7. MOD-DEF 1, 2: These pins are definition pins for the TXN31015D2 Optical Transceiver. They are pulled up with a 4.7 K - 10 K W resistor on the host board. Use a pull-up voltage between 2.0 V and VccT, R+0.3 V. * MOD-DEF 1 is the clock line of a 2-wire serial interface for serial ID. * MOD-DEF 2 is the data line of a 2-wire serial interface for serial ID. 8. TX FAULT is a TTL output and has an internal 10k pull-up resistor to VccT. * Low: Indicates normal operation. In the low state, the output is pulled to < 0.8 V. * High: Indicates a laser fault.
Figure 1 shows the TXN31015D2 Optical Transceiver electrical interface pin numbers.
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 13
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Figure 1.
Pin Layout
B5000-01
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 14
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
4.0
4.1
Termination
Types of I/O Interfaces
The TXN31015D2 Optical Transceiver has the following types of I/O interfaces. * CML interface * TTL interface High-speed I/Os use the CML interface, while control signals use the TTL interface. Proper termination of I/Os is required for good signal integrity. If I/Os (particularly the CML I/Os) are not terminated properly, then jitter increases significantly due to reflection from impedance mismatches.
4.2
CML Termination
Figure 2 shows a circuit diagram for the CML termination for the TXN31015D2 Optical Transceiver receiver output. The TXN31015D2 Optical Transceiver has built in ACcoupling capacitors, which help prevent a direct current path from the TXN31015D2 Optical Transceiver power supply to the SerDes input. (A direct current path could damage the ESD diodes on the SerDes.) * Internal termination. For the TXN31015D2 Optical Transceiver receiver output, the SerDes interface provides an internal termination resistor. * External termination. For the proper external termination of the SerDes interface, refer to the SerDes specification.
Figure 2.
Circuit Diagram for CML Termination on Receiver Output
3.3 V 50
AC-coupling capacitor
100
Receiver Output
SerDes Input
B3243-02
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 15
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Figure 3 shows a circuit diagram for the CML termination for the TXN31015D2 Optical Transceiver transmitter input. Internal termination. The TXN31015D2 Optical Transceiver transmitter input has an internal 100 termination between two inputs. AC-coupling capacitors are also built into the TXN31015D2 Optical Transceiver. Figure 3. Circuit Diagram for CML Termination on Transmitter Input
3.3 V
AC-Coupling Capacitor
100
Transmitter Input
SerDes Output
B3244-02
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 16
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
5.0
Table 11.
SFF Timing Parameters
Table 11 lists the timing parameters for SFF management. Timing Parameters for SFF Management
Parameter TX_DISABLE assert time Symbol t_off Min - Max 10 Unit s Conditions Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal Time from power on or negation of TX_FAULT using TX_DISABLE Time from fault to TX_FAULT ON Time TX Disable must be held high to reset TX_FAULT Time from non-Signal Detect state to RX_Signal Detect Assert Time from Signal Detect state to RX_non-Signal Detect De-assert -
TX_DISABLE negate time Time to initialize includes reset of TX_FAULT TX_FAULT Assert Time TX Disable to reset RX_Signal Detect Assert time RX_Signal Detect Deassert time Serial ID Clock Rate
t_on
-
1
ms
t_init t_fault t_reset t_sd_on
- - 10 -
300 100
ms s s
100
s
t_sd_off f_serial_clock
- -
100 100
s kHz
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
6.0
Digital Diagnostic Monitoring Interface
This section includes the following topics: * Section 6.1, "Overview of Digital Diagnostic Monitoring Interface" on page 18 * Section 6.2, "General Memory Map Descriptions" on page 19 * Section 6.3, "Alarm and Warning Fields for 2-Wire Interface Address A2h" on page 20 * Section 6.4, "A/D Fields for 2-Wire Interface Address A2h" on page 22
6.1
Overview of Digital Diagnostic Monitoring Interface
The TXN31015D2 Optical Transceiver supports the 2-wire serial communication protocol. The TXN31015D2 Optical Transceiver has a digital diagnostic monitoring interface that is an extension of the serial ID interface defined in the Gigabit Interface Converter (GBIC) specification and the SFF Transceiver MultiSource Agreement (MSA) referenced in Section 1.0, "Introduction" on page 7. * Standard SFF serial ID interface. The standard SFF serial ID interface (the memory map for which is in Table 12, "Memory Map - 2-Wire Address Range Descriptions" on page 19) provides access to identification information using the 8bit address 1010000X (A0h). The serial identification information describes information such as the following for the TXN31015D2 Optical Transceiver: capabilities, standard interfaces, and manufacturer information. * Digital diagnostic monitoring interface. The digital diagnostic monitor interface (the memory map for which is in Table 12, "Memory Map - 2-Wire Address Range Descriptions" on page 19) is an extension of the standard serial ID interface. This interface, which uses the 8-bit address 1010001X (A2h) reserved for optical transceivers, allows real-time access to device-operating parameters while leaving unchanged the original serial ID memory map A0h. The digital diagnostic monitoring interface is backward compatible with both the GBIC specification and the SFF MSA.
Note:
For details on the 2-wire addresses A0h and A2h, refer to the SFF-8472 document referenced in Section 1.0, "Introduction" on page 7.
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 18
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
6.2
General Memory Map Descriptions
Table 12 lists descriptions of address ranges for the serial ID memory map. * The 2-wire address A0h contains serial ID information defined by the SFF MSA. * The 2-wire address A2h contains data related to the digital diagnostics, defined by the SFF-8472 document referenced in Section 1.0, "Introduction" on page 7.
Table 12.
Memory Map - 2-Wire Address Range Descriptions
2-Wire Address 1010000X (A0h) Address Range Address Range Description (Standard Serial ID Information) Address Range 0-39 0-95 Serial ID Defined SFF MSA (96 bytes) 40-95 2-Wire Address 1010001X (A2h) Address Range Description (Digital Diagnostics Information) Alarm and Warning (40 bytes) For details, see Table 13, "Alarm and Warning Fields - 2-Wire Address A2h, Address 0-95". Vendor Specific / Calibration Constants (56 bytes) For details, see Table 13, "Alarm and Warning Fields - 2-Wire Address A2h, Address 0-95". Real Time Digital Diagnostics Interface (24 bytes) For details, see the following: * Table 14, "A/D Fields - 2-Wire Address A2h, Addresses 96-109" on page 22 * Table 15, "A/D Status/Control Bits - 2Wire Address A2h, Address 110" on page 22 Vendor Specific (8 bytes) User Writable EEPROM (120 bytes) Vendor Specific (8 bytes)
96-127
Vendor Specific (32 bytes)
96-119
120-127 128-255 Reserved in SFF MSA (128 bytes) 128-247 248-255
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Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
6.3
Alarm and Warning Fields for 2-Wire Interface Address A2h
Table 13 is a more detailed memory map of the 2-wire interface address A2h for the Alarm and Warning fields, address range 0 to 95.
Table 13.
Alarm and Warning Fields - 2-Wire Address A2h, Address 0-95 (Sheet 1 of 2)
Data Address Field Size (Bytes) Field Name Base ID Fields 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Temperature High alarm LSB Temperature Low alarm LSB Temperature High Warning LSB Temperature Low Warning LSB Vcc High Alarm LSB Vcc Low Alarm LSB Vcc High Warning LSB Vcc Low Warning LSB Bias High Alarm LSB Bias Low Alarm LSB Tx Bias High Warning LSB Tx Bias Low Warning LSB Tx Power High Alarm LSB Tx Power Low Alarm LSB Tx Power High Warning LSB Tx Power Low Warning LSB Rx Power High Alarm LSB MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address Field Description
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 20
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Table 13.
Alarm and Warning Fields - 2-Wire Address A2h, Address 0-95 (Sheet 2 of 2)
Data Address 34 35 36 37 38 39 40-55 56-95 Field Size (Bytes) 1 1 1 1 1 1 16 40 Field Name Rx Power Low Alarm LSB Rx Power High Warning LSB Rx Power Low Warning LSB Vendor-Specific Calibration Constants Field Description MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address MSB at low address - -
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 21
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
6.4
A/D Fields for 2-Wire Interface Address A2h
Table 14 lists descriptions of the analog-to-digital (A/D) fields for the 2-wire interface address A2h, data addresses 96 to 109.
Table 14.
A/D Fields - 2-Wire Address A2h, Addresses 96-109
Data Address 96 97 98 99 100 101 102 103 104 105 106-109 Field Size (Bytes) 1 1 1 1 1 1 1 1 1 1 4 Field Name Field Description Signed 2's complement integer C (-40 to +125). Based on internal temperature measurement. Fractional part of temperature (count/256) Internally measured supply voltage in transceiver. Voltage reading is full 16-bit value x 100 Volt. (Yields range of 0 to 6.55V) Measured Laser Bias Current in mA. Bias current is full 16-bit value x 2 A. (Full range of 0 to +131 mA) Measure TX output power in mW. TX power is full 16-bit value x 0.1 W. (Full range of -40 to +8.2 dBm) Measured RX input power in mW. RX power is full 16-bit value x 0.1 W. (Full range of -40 to +8.2dBm) -
Temperature MSB Temperature LSB Vcc MSB Vcc LSB TX Bias MSB TX Bias LSB TX power MSB TX power LSB RX Power MSB RX Power LSB Reserved
Table 15 lists descriptions of the A/D status/control bits for the 2-wire interface address A2h, data address 110. Table 15. A/D Status/Control Bits - 2-Wire Address A2h, Address 110
Data Address 110 110 110 Bit 2 1 0 Tx Fault SD Data Ready Bar Bit Name Bit Description Digital State of Tx Fault Output Digital State of Signal Detect. This bit is set when nonSignal Detect, it is cleared in normal operation. Indicates transceiver has achieved power up and is ready.
7.0
Grounding Scheme
There are two types of grounding on the TXN31015D2 Optical Transceiver. * Chassis ground. The LC "nose" and the TXN31015D2 Optical Transceiver housing chassis comprise the chassis ground, which is used to connect to the system chassis ground. * Signal ground. On the TXN31015D2 Optical Transceiver, there are two separate signal grounds. The Receiver Ground pin (pin 1) on the TXN31015D2 Optical Transceiver is connected to the internal TXN31015D2 Optical Transceiver RX signal ground. The Transmitter Ground pin (pin 7) on the TXN31015D2 Optical Transceiver is connected to the internal TXN31015D2 Optical Transceiver TX signal ground.
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 22
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
The chassis ground and the signal ground are separated to prevent ESD from the main chassis ground moving directly to the TXN31015D2 Optical Transceiver. For good EMI and ESD performance, Intel recommends connecting these two signal grounds as follows: * Connect Pin 1 to the RX signal ground on the host board adaptor (HBA) printed circuit board. * Connect Pin 7 to the TX signal ground on the HBA printed circuit board. Figure 4 shows a grounding application diagram for the TXN31015D2 Optical Transceiver. Proper grounding is critical for good EMI and ESD performance.
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 23
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Figure 4.
Grounding Application Diagram for Intel(R) TXN31015D2 Optical Transceiver
HBA PCB
PC Mount Chassis Ground
LC Nose Chassis Ground
Side View
Transceiver Housing Chassis Ground HBA PCB
PC Mount Chassis Ground
Front Posts Chassis Ground RX Signal Ground
Front Posts Chassis Ground
Bottom View
CA1234 5 D B 10 9 8 7 6
Front Posts Chassis Ground
TX Signal Ground
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 24
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
8.0
Mechanical Specification
Figure 5 shows the TXN31015D2 Optical Transceiver SFF mechanical specifications. The dimensions comply with the SFF Multisource Agreement (MSA).
Note:
Aqueous wash is not applicable for this product.
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 25
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Figure 5.
SFF Mechanical Specifications
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 26
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
9.0
Regulatory Compliance
This section discusses the following topics: * Section 9.1, "Electromagnetic Compatibility Compliance" on page 27 * Section 9.2, "Safety Compliance" on page 28 * Section 9.3, "Lead-Free Conformance" on page 29 * Section 9.4, "Compliance with Restriction of Hazardous Substances (RoHS)" on page 29 * Section 9.5, "Management Methods on Control of Pollution from Electronic Information Products (a.k.a. China RoHS)" on page 30 * Section 9.6, "Product Certification Markings and Compliance Statements" on page 31
9.1
Electromagnetic Compatibility Compliance
Table 16 lists emissions and immunity regulations with which the TXN31015D2 Optical Transceiver complies when tested in a representative chassis.
Table 16.
Electromagnetic Compatibility Compliance
Requirement * Electromagnetic interference (EMI) * Regulation FCC rules, Part 15, subpart B EN 55022 Performance Level Meets Class B limits with a minimum 6 dB margin 2 kV contact discharge to connector electrical pins with no degradation in performance or loss of function 15 kV air discharge 8 kV contact discharge to face plate Meets Level B test criteria (that is, no degradation of performance or loss of function occurs). Note: Actual ESD may vary, depending on system configuration. * *
JEDEC JESD22-A114-B Human Body Model
Electrostatic discharge (ESD) EN 61000-4-2
Radio frequency electromagnetic field (Radiated immunity)
EN 61000-4-3, Level A test criteria
10 V/m from 80 MHz to 1 GHz with no degradation of performance or loss of function
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 27
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
9.2
Safety Compliance
Table 17 lists and describes the relevant safety regulations with which the TXN31015D2 Optical Transceiver complies.
Table 17.
Safety Compliance
Requirement Regulation UL 60950-1 CSA C22.2 No. 60950-1 EN 60950-1+A11 Product Safety IEC 60950-1 GR-63-CORE Section 4.2, Clause 4.2.3.1 Title Information Technology Equipment - Safety - Part 1: General Requirements (USA and Canada) Information Technology Equipment - Safety - Part 1: General Requirements (European Union) Information Technology Equipment - Safety - Part 1: General Requirements (International) Compliant with the fire resistance requirements of Telcordia Technologies Generic Requirements GR-63-CORE document for discrete electronic components. Title 21 Chapter I Subchapter J - Radiological Health Part 1040: Performance Standards for Light-Emitting Products Safety of Laser Products - Part 1: Equipment Classification, Requirements and User's Guide Safety of Laser Products - Part 1: Equipment Classification, Requirements and User's Guide Safety of Laser Products - Part 2: Safety of Optical Fiber Communication Systems Safety of Laser Products - Part 2: Safety of Optical Fiber Communication Systems
21CFR1040.10
EN 60825-1+A1 +A2 Laser Safety IEC 60825-1+A1 +A2 EN 60825-2 IEC 60825-2
Caution:
This device is a Class 1 laser product for use only under the recommended operating conditions and ratings specified in this document.
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 28
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
9.3
Lead-Free Conformance
The TXN31015D2 Optical Transceiver uses a lead-free assembly, although certain discrete components within the assembly may contain lead, being necessary for either component performance or reliability. The TXN31015D2 Optical Transceiver is referred to as a "Lead-free 2nd Level Interconnect." The enclosure, circuit board substrate, and the solder connections from the circuit board to the components (second-level connections) are all lead-free. Table 18 lists various forms of the "Lead-Free 2nd Level Interconnect" marking for the TXN31015D2 Optical Transceiver and accompanying collateral.
Table 18.
Lead-Free 2nd-Level Interconnect Markings
Description Marking
Lead-Free 2nd Level Interconnect: The Lead-Free 2nd Level Interconnect symbol is used to identify electrical and electronic assemblies and components in which the lead (Pb) concentration level in the circuit board substrate and the solder connections from the circuit board to the components (second-level interconnect) are not greater than 0.1% by weight (1000 ppm). Note: Any of the three symbols shown may be used, as space permits.
or
or
9.4
Compliance with Restriction of Hazardous Substances (RoHS)
This product complies with the European Union directive for Restriction of Hazardous Substances (RoHS) - Restriction on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment, Directive 2002/95/EC plus amendments. However, certain discrete components do contain lead (an RoHS-restricted substance) in amounts that exceed threshold concentration levels. This product uses the following applicable RoHS technology exemptions: * Lead in optical and filter glass * Lead in glass of electronic components Note: RoHS implementation details are subject to change. This product is RoHS 6 compliant, defined as complying with the restriction for all six listed substances by meeting strict threshold levels for those substances or through the use of the applicable exemptions listed above.
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 29
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
9.5
Management Methods on Control of Pollution from Electronic Information Products (a.k.a. China RoHS)
Table 19.
Hazardous Substances Table
(Parts) (Hazardous Substance)
(Pb)
(Hg)
(Cd)
(Cr(VI))
(PBB)
(PBDE)
Integrated optical circuit board
assembly
x

Metal enclosure
SJ/T 113632006
Indicates that this hazardous substance contained in all homogeneous materials of this part is below the
limit requirement in SJ/T 11363-2006.
xSJ/T 113632006
xIndicates that this hazardous substance contained in at least one of the homogeneous materials of this
part is above the limit requirement in SJ/T 11363-2006.
,
This table shows where these substances may be found in the supply chain of our electronic information products, as of the date of sale of the enclosed product. Note that some of the component types listed above may or may not be a part of the enclosed product.
,. .
The Environment-Friendly Use Period (EFUP) for all enclosed products and their parts are per the symbol shown here, unless otherwise marked. The Environment-Friendly Use Period is valid only when the product is operated under the conditions defined in the product manual.
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 30
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
9.6
Product Certification Markings and Compliance Statements
Table 20 lists the TXN31015D2 Optical Transceiver product certification markings and compliance statements.
Table 20.
Product Certification Markings and Compliance Statements
Origin and Description Markings CE mark. The CE (Conformite Europeene*) mark indicates compliance to the European Union Low Voltage directive (2006/95/EC, formerly 73/23/EEC). TUV Rheinland type approval mark for components and subassemblies for the European Union. The Technischer Uberwachungsverein* (TUV - German for "Technical Inspection Association") Rheinland type approval mark is for components and subassemblies for the European Union. Where space does not permit, the smaller alternate TUV mark (see the next row in this table) may be used. TUV Rheinland type approval mark for components and subassemblies for the European Union - Alternate. This alternate mark may be used where space constraints exist that do not permit use of the TUV Rheinland mark in the previous row of this table. Alternate TUV mark: Markings and Compliance Statements
UL Recognized Component mark for the USA and Canada.
China Environmental Friendly Use Period (EFUP) mark, where 30 in the marking denotes 30 years.
Compliance Statements USA Food and Drug Administration (FDA), Center for Devices and Radiological Health compliance statement. USA FDA, Center for Devices and Radiological Health compliance statement - Alternate. Use the alternate statement listed, as needed. Complies with 21CFR 1040.10 except for deviations pursuant to Laser Notice No. 50, dated July 26, 2001. Alternate FDA compliance statement: Complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No. 50, dated July 26, 2001.
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 31
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
10.0
Table 21.
Ordering Information
Table 21 lists ordering information for the TXN31015D2 Optical Transceiver. Ordering Information
Product Number TXN31015D200xxx1 MM Number 874474 Description Quad-rate 4/2/1 Gbps Fibre Channel and Gigabit Ethernet SFF module with digital diagnostics feature compliant with RoHS 6
1. The last 3 characters of the part number ("xxx") are used to designate customer-specific customization. The Intel standard part has "000" as the last three characters.
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 32
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
11.0
Table 22.
Acronyms
Acronyms
Acronym A/D BER CFR CML EMI ESD EU FC-PI FCC FDA GBIC IEC IEEE LOS MMF MSA NRZ Pb PCB PRBS RFI SFF SCSI SONET TOSA TTL TUV UL VCSEL Analog-to-Digital Bit Error Rate Code of Federal Relations Current Mode Logic Electro-Magnetic Interference Electro-Static Discharge European Union Fibre Channel - Physical Interfaces Federal Communications Commission Food and Drug Administration GigaBit Interface Converter International Electrotechnical Commission Institute of Electrical and Electronics Engineers Loss of Signal Multimode Fiber Multisource Agreement Non-Return to Zero Lead Printed Circuit Board Pseudo Random Bit Sequence Radio Frequency Immunity Small-Form Factor Small Computer System Interface Synchronous Optical Network Transmitter Optical Sub-Assembly Transistor-Transistor Logic Technischer Uberwachungsverein Underwriter Laboratories* Vertical Cavity Surface Emitting Laser Meaning
18-April-2007 Order Number: 316366, Revision: 001US
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 33
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible
Intel(R) TXN31015D2 Quad-Rate 850 nm Optical Transceiver - SFF* MSA Compatible Datasheet 34
18-April-2007 Order Number: 316366, Revision: 001US

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